1. Field of the Invention
The present invention relates to the technical field of flat panel display device, and in particular to a thin-film transistor (TFT) active device.
2. The Related Arts
In an active matrix flat panel display, each pixel point is driven by a thin-film transistor (TFT) active device integrated on the rear side of the pixel point so as to achieve displaying screen message in high speed, high brightness, and high contrast. Each pixel point of the active matrix flat panel display is controlled by the TFT integrated therewith and is thus an active pixel point, whereby the speed is greatly increased and contrast and brightness are both significantly improved and at the same time, the resolution may reach a very high level. For the whole device of flat panel display, the TFTs (matrix) may apply active control over each independent pixel of the screen. This is the origin of the term “active matrix TFT”. The active matrix flat panel display has effectiveness that is close to a CRT display and is the main stream displays for modern notebook computers and desktop computers.
Referring to FIG. 1, a flow of a typical manufacture process of an oxide semiconductor TFT having an etch stop layer structure is shown, structures that can be formed in the same manufacture step bear the same cross hatching in the drawing. An oxide semiconductor TFT is a technique based on TFT driving that arranges a metal oxide active layer on a gate insulation layer of TFT. The oxide active layer is preferably an IGZO layer, wherein IGZO is an abbreviation standing for indium gallium zinc oxide. According to the flow of manufacture process shown in FIG. 1, a gate electrode (GE) 10 is first formed on a substrate. Next, a gate insulation (GI) layer 11 is formed on and covers the gate electrode 10. Then, an oxide semiconductor layer 12, which is specifically an IGZO layer, is formed on the gate insulation layer 11. Then, an etch stop (ES) layer 13 is formed on the oxide semiconductor layer 12. The ES layer is often formed through chemical vapor deposition (CVD) of a precursor substance. Afterwards, a source/drain (S/D) electrode 14 is formed to electrically connect with the oxide semiconductor layer 12 and etching is applied to form source electrode and drain electrode respectively. Next, a passivation (PV) layer 15 is formed to cover the source/drain electrode 14. To this point, a TFT active device that is composed of the gate electrode 10, the gate insulation layer 11, the oxide semiconductor layer 12, the etch stop layer 13, the source/drain electrode 14, and the passivation layer 15 is completed. Further, in the flow of manufacture process shown in FIG. 1, a subsequent operation is forming an indium tin oxide (ITO) electrode 16 to serve as a pixel electrode to eventually form a TFT applicable to an active matrix flat panel display.
Referring to FIG. 2, a schematic view is given to show a typical TFT active device manufactured with oxide semiconductor TFT by means of copper process is given. The TFT active device generally comprises a gate terminal, a gate insulation layer 21, an oxide semiconductor layer 22, an etch stop layer 23, a source/drain electrode 24, and a passivation layer 25. The oxide semiconductor layer 22 is formed on the gate insulation layer 21. The etch stop layer 23 is formed on the oxide semiconductor layer 22. The source/drain electrode 24 is electrically connected to the oxide semiconductor layer 22. The passivation layer 25 covers the source/drain electrode 24. In the copper process, to avoid penetration of copper ions, a barrier layer 27 must be first deposited before copper is deposited and the current solution includes Mo, Ti, or similar alloys or compounds. Although the barrier layer 27 is arranged between the source/drain electrode 24 and the oxide semiconductor layer 22 and the etch stop layer 23, yet Cu ions may still easily penetrate the passivation layer 25 and the etch stop layer 23 to diffuse into the oxide semiconductor layer 22, causing abnormalities, such as threshold voltage shift, mobility down, and sub-threshold swing degradation.
Referring to FIG. 3, a plot is given for comparison of gate voltage (VG)-drain current (ID) characteristic curves before and after air annealing adopted in a conventional manufacture process that uses IGZO TFT in combination with copper process. The plot is copied from JJAP 51 (2012) 011401. After the air annealing, the effect of copper ion diffusion significantly alert the gate voltage (VG)-drain current (ID) characteristic curve, namely causing abnormalities such as threshold voltage shift, mobility down, and sub-threshold swing degradation.
As shown in the following Table 1, a comparison is given for materials of GI/ES/PV layers that are commonly used in the manufacture process that uses oxide semiconductor TFT in combination with copper process. One case uses SiOx as an insulation material, wherein SiH4+N2O is used as a precursor for CVD and forms the GI/ES/PV layers through CVD to provide TFT of excellent properties, but copper ions may easily diffuse. Another case uses SiNx as an insulation material, wherein SiH4+NH3+N2 is used as a precursor for CVD and forms the GI/ES/PV layers through CVD, wherein the insulation material contains relatively high contents of hydrogen and the TFT obtained does not show good property, but copper ions may not easily diffuse.
TABLE 1Comparison for conventionally used materials of GI/ES/PV layersMaterial ofCopper IonGI/ES/PV LayerCVD PrecursorTFT PropertyResistanceSiOxSiH4 + N2OGoodPoorSiNxSiH4 + NH3 + N2PoorGood
Thus, the conventional manufacture process using oxide semiconductor TFT in combination with copper process will face dual influences of diffusion of metal ions from metal electrodes and H contents of GI/ES/PV layers. Both factors are keys that control the stability of the TFT device.